I put a blog entry up on the Oasys blog about their new release, which is the first to support VHDL. But a couple of people told me it was a nice recounting of history so I decided to put a more ...

The data objects in VHDL and Verilog form expression operands. Knowing the operand differences between the two HDLs helps you write more efficient chip-design code. Expressions consist of operators ...

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...

Esperan is running its project-based HDL training courses through June and July. The aim, says the training company, is to allow designers to implement their project in hardware using supplied ...

The growing complexity of SoCs and the reduced life cycle of electronic products demand higher levels of design productivity while meeting compressed development schedules. The reuse of design IP ...

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog ...

The latest version of Accellera’s Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, unifies the standard’s previous version with IEEE Std. 1364-2005, the Verilog hardware description ...